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o0808 ms / 22807 ms pc 20061227-s00002 no.a0662-1/11 http://onsemi.com stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty. semiconductor components industries, llc, 2013 may, 2013 lb11620t overview the lb11620t is a direct pwm drive predriver ic that is optimal for three-phase power brushless motors. a motor driver circuit with the desired output capability (voltage and current) can be implemented by adding discrete transistors or other power devices to the outputs of this ic. since the lb11620t is provided in a miniature package, it is also appropriate for use with miniature motors as well. features ? three-phase bipolar drive ? direct pwm drive (input of either a control voltage or a variable-duty pwm signal) ? built-in forward/reverse switching circuit ? full complement of protection circuits (current limiter, low-voltage, and automatic recovery lock (motor constraint) protection circuits) ? selectable hall sensor signal pulse output specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit supply voltage 1 v cc max v cc pin 18 v output current i o max ul, vl, wl, uh, vh, wh pins 30 ma allowable power dissipation pd max *mounted on a circuit board. 0.8 w operating temperature topr -20 to +100 c storage temperature tstg -55 to +150 c * mounted on a circuit board : 114.3mm 76.1mm 1.6mm, glass epoxy board. monolithic digital ic brushless motor driver orderin g numbe r : ena0662a
lb11620t no.a0662-2/11 recommended operating ranges at ta = 25 c parameter symbol conditions ratings unit supply voltage range 1-1 v cc 1-1 v cc pin 8 to 17 v supply voltage range 1-2 v cc 1-2 v cc pin, with v cc shorted to vreg 4.5 to 5.5 v output current i o ul, vl, wl, uh, vh, wh pins 25 ma 5 v constant voltage output current ireg -30 ma hp pin voltage vhp 0 to 17 v hp pin output current ihp 0 to 15 ma rd pin voltage vrd 0 to 17 v rd pin output current ird 0 to 15 ma electrical characteristics at ta = 25 c, v cc = 12v ratings parameter symbol conditions min typ max unit supply voltage 1 i cc 1 12 16 ma 5v constant voltage output (vreg pin) output voltage vreg 4.7 5.0 5.3 v line regulation vreg1 v cc = 8 to 17v 40 100 mv load regulation vreg2 i o = -5 to -20ma 10 30 mv temperature coefficient vreg3 design target 0 mv/ c low-voltage protection circuit (vreg pin) operating voltage vsdl 3.5 3.7 3.9 v clear voltage vsdh 3.95 4.15 4.35 v hysteresis vsd 0.3 0.45 0.6 v output block output voltage 1-1 v out 1-1 low level i o = 400 a 0.2 0.5 v output voltage 1-2 v out 1-2 low level i o = 10ma 0.9 1.2 v output voltage 2 v out 2 high level i o = -20ma v cc -1.1 v cc -0.9 v output leakage current i o leak 10 a hall amplifier block input bias current ihb (ha) -2 -0.5 a common-mode input voltage range 1 vicm1 when a hall effect sensor is used 0.5 v cc -2.0 v common-mode input voltage range 2 vicm2 for single-sided input bias (hall ic application) 0 v cc v hall input sensitivity 80 mvp-p hysteresis v in (ha) 15 24 40 mv input voltage low high vslh (ha) 5 12 20 mv input voltage high low vshl (ha) -20 -12 -5 mv pwm oscillator (pwm pin) high-level output voltage v oh (pwm) 2.75 3.0 3.25 v low-level output voltage v ol (pwm) 1.2 1.35 1.5 v external capacitor charge current ichg vpwm = 2.1v -120 -90 -65 a oscillator frequency f (pwm) c = 2000pf 22 khz amplitude v (pwm) 1.4 1.6 1.9 vp-p continued on next page
lb11620t no.a0662-3/11 continued from preceding page. ratings parameter symbol conditions min typ max unit ei+ pin input bias current ib (ctl) -1 1 a common-mode input voltage range vicm 0 vreg-1.7 v input voltage 1 vctl1 output duty 100% 3.0 v input voltage 2 vctl2 output duty 0% 1.35 v input voltage 1l vctl1l design target value. when vreg = 4.7v, 100% 2.82 v input voltage 2l vctl2l design target value. when vreg = 4.7v, 0% 1.29 v input voltage 1h vctl1h design target value. when vreg = 5.3v, 100% 3.18 v input voltage 2h vctl2h design target value. when vreg = 5.3v, 0% 1.44 v hp pin output saturation voltage vhpl i o = 10ma 0.2 0.5 v output leakage current ihpleak v o = 18v 10 a csd oscillator (csd pin) high-level output voltage v oh (csd) 2.7 3.0 3.3 v low-level output voltage v ol (csd) 0.7 1.0 1.3 v external capacitor charge current ichg1 vcsd = 2v -3.15 -2.5 -1.85 a external capacitor discharge curre nt ichg2 vcsd = 2v 0.1 0.14 0.18 a charge/discharge current ratio rcsd charge current /discharge current 15 18 21 times rd pin low-level output voltage vrdl i o = 10ma 0.2 0.5 v output leakage current il (rd) v o = 18v 10 a current limiter circuit (rf pin) limiter voltage vrf rf -gnd 0.225 0.25 0.275 v pwmin pin input frequency f (pi) 50 khz high-level input voltage v ih (pi) 2.0 vreg v low-level input voltage v il (pi) 0 1.0 v input open voltage v io (pi) vreg-0.5 vreg v hysteresis v is (pi) 0.2 0.25 0.4 v high-level input current i ih (pi) vpwmin = vreg -10 0 10 a low-level input current i il (pi) vpwmin = 0v -130 -90 a f/r pin high-level input voltage v ih (fr) 2.0 vreg v low-level input voltage v il (fr) 0 1.0 v input open voltage v io (fr) vreg-0.5 vreg v hysteresis v is (fr) 0.2 0.25 0.4 v high-level input current i ih (fr) -10 0 10 a low-level input current i il (fr) -130 -90 a n1 pin high-level input voltage v ih (n1) 2.0 vreg v low-level input voltage v il (n1) 0 1.0 v input open voltage v io (n1) vreg-0.5 vreg v high-level input current i ih (n1) vn1 = vreg -10 0 10 a low-level input current i il (n1) vn1 = 0v -130 -100 a
lb11620t no.a0662-4/11 package dimensions unit : mm (typ) 3260a pin assignment 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 lb11620t in1 + in2 - in2 + in1 - ul uh vl vh wl wh rf gnd pwm in3 + in3 - rd csd pwmin f/r hp n1 ei + vreg v cc ? three-phase logic truth table (in = ?h? indicates the state where in + > in - ) f/r = ?l? f/r=?h? output in1 in2 in3 in1 in2 in3 pwm 1 h l h l h l vh ul 2 h l l l h h wh ul 3 h h l l l h wh vl 4 l h l h l h uh vl 5 l h h h l l uh wl 6 l l h h h l vh wl ? pwmin pin input state state high or open output off low output on if the pwm pin is not used, the inpu t must be held at the low level. ? n1 pin input state hp output high or open three hall sensor synthesized output low single hall sensor output sanyo : tssop24(225mil) 6.4 0.5 4.4 (0.5) (1.0) 6.5 0.5 0.15 1 12 24 13 0.22 0.08 1.2max 0 0.8 0.32 0.4 1.2 ? 20 80 100 60 20 40 012 0 ambient temperature, ta ? c allowable power dissipation, pd max ? w pd max ? ta specified circuit board : 114.3 76.1 1.6mm 3 glass epoxy board mounted on a circuit board
lb11620t no.a0662-5/11 pin functions pin no. pin description 1 gnd ground 2 rf output current detection. the current detection resistor (rf) voltage is sensed by th e rf pin to implement current detection. the maximum output current is set by rf to be iout = 0.25/rf. 7 5 3 uh vh wh outputs (pwm outputs). these are push-pull outputs. 8 6 4 ul vl wl outputs these are push-pull outputs. 10, 9 12, 11 14, 13 in1 + , in1 - in2 + , in2 - in3 + , in3 - hall sensor inputs from each motor phase. the logic high state indicates that in + > in - . if inputs are provided by a hall effect sensor ic, the comm on-mode input range is expanded by biasing either the + or - input. 15 pwm functions as both the pwm oscillator frequency setting pin and the initial reset pulse setting pin. connect a capacitor between this pin and ground. 16 rd lock (motor constrained) detection state output. this output is turned on when the motor is turning and off when the lock protection function detects that the motor has bee n stopped. this is an open collector output. 17 csd sets the operating time fo r the lock protection circuit. connect a capacitor between this pin and ground. connect this pi n to ground if the lock protection function is not used. 18 pwmin pwm pulse signal input. the output goes to the drive st ate when this pin is low, and to the off state when this pin is high or open. to use this pin for control, a ctl amplifier input such that the toc pin voltage goes to the 100% duty state must be provided. 19 f/r forward/reverse control input 20 hp hall signal output (hp output). this pr ovides either a single hall sensor output or a synthesized 3-sensor output. 21 n1 hall signal output (hp output) selection 22 ei+ ctl amplifier + (noninverting) input. the pwmin pin must be held at the low level to use this input for motor control 23 vreg 5v regulator output (used as the control circuit pow er supply. a low-voltage protection circuit is built in.) connect a capacitor between this pin and ground for stabilization. 24 v cc power supply. connect a capacitor between this pin and gr ound to prevent noise and other disturbances from affecting this ic.
lb11620t no.a0662-6/11 hall sensor signal input/output timing chart f/r = " l " in1 in2 in3 uh ul vl wl wh vh f/r = " h " in1 in2 in3 uh ul vl wl sections shown in gray are pwm output periods. wh vh
lb11620t no.a0662-7/11 block diagram and application example 1 bipolar transistor drive (high side pwm) using a 5v power supply vm 5v gnd v cc rf wl vl ul uh vreg v cc vh wh + - in3 + ctl vreg hp ei + pwm pwmin + + + pwm osc pwm in pri driver curr lim control logic vreg lvsd comp csd osc rd f/r n1 hp logic hall hys amp in2 + in1 + in1 f/r in3 - in2 - in1 - vreg rd csd hall logic
lb11620t no.a0662-8/11 application example 2 54 mos transistor drive (low side pwm) using a 12v single-voltage power supply vm(12v) gnd tr tr tr v cc rf wh vh uh ul vreg v cc vl wl + - in3 + vreg hp ei + pwm pwmin + + pwm osc pwm in pri driver curr lim control logic vreg lvsd comp csd osc rd f/r n1 hp logic hall hys amp in2 + in1 + in1 f/r in3 - in2 - in1 - vreg rd csd hall logic
lb11620t no.a0662-9/11 application example 3 mos transistor drive (low side pwm) using a v cc = 12v, vm = 24v power supply system v cc (12v) gnd v cc rf wh vh uh ul vreg v cc vl wl + - in3 + vreg hp ei + pwm pwmin + vm(24v) + + pwm osc pwm in pri driver curr lim control logic vreg lvsd comp csd osc rd f/r n1 hp logic hall logic hall hys amp in2 + in1 + in1 f/r in3 - in2 - in1 - vreg rd csd
lb11620t no.a0662-10/11 application example 4 mos transistor drive (low side pwm) using a 24v single-voltage power supply gnd v cc rf wh vh uh ul vreg v cc vl wl + - in3 + vreg hp ei+ pwm pwmin + vm(24v) + pwm osc pwm in pri driver curr lim control logic vreg lvsd comp csd osc rd f/r n1 hp logic hall logic hall hys amp in2 + in1 + in1 f/r in3 - in2 - in1 - vreg rd csd
lb11620t no.a0662-11/11 current detection resistor to the rf pin pulse input to the pwmin pin lb11620t functional description 1. output drive circuit the lb11620t adopts direct pwm drive to minimize power loss in the outputs. the output transistors are always saturated when on, and the motor drive power is adjusted by changing the on duty of the output. the output pwm switching is performed on the uh, vh, and wh outputs. since the ul to wl and uh to wh outputs have the same output form, applications can select either low side pwm or high side pwm drive by changing the way the external output transistors are connected. since the reverse recovery time of the diodes connected to the non-pwm side of the outputs is a problem, these devices must be selected with care . (this is because through currents will flow at the instant the pwm side transistors turn on if diodes with a short reverse recovery time are not used.) 2. current limiter circuit the current limiter circuit limits the output current peak value to a level determined by the equation i = vfr/rf (vrf = 0.25v typical, rf: current detection resistor). this circuit suppresses the output current by reducing the output on duty. the current limiter circuit includes an internal filter circuit to prevent incorrect current limiter circuit operation due to detecting the output diode reverse recovery current due to pwm oper ation. although there should be no problems with the internal filter circuit in normal applications, applications should add an external filter circuit (such as an rc low-pass filter) if incorrect operation occurs (if the diode reverse recovery current flows for longer than 1 s). 3. notes on the pwm frequency the pwm frequency is determined by the ca pacitor c (f) connected to the pwm pin. f pwm 1/(22500 c) if a 2000pf capacitor is used, the circuit will oscillate at about 22khz. if the pwm freque ncy is too low, switching noise will be audible from the motor, and if it is too high, the output power loss will increase. thus a frequency in the range 15k to 50khz must be used. the ca pacitor's ground terminal must be pl aced as close as possible to the ic?s ground pin to minimize the influence of output noise and other noise sources. 4. control methods the output duty can be controlled by either of the following methods ? control based on comparing the ei+ pin voltage to the pwm oscillator waveform the low side output transistor duty is determined according to the result of comparing the ei+ pin voltage to the pwm oscillator waveform. when the ei+ pin voltage is 1.35v or lo wer, the duty will be 0%, and when it is 3.0v or higher, the duty will be 100%. when ei+ pin voltage control is used, a low-level input must be applied to the pwmin pin or that pin connected to ground. ? pulse control using the pwmin pin a pulse signal can be input to the pwmin pin, and the output can be controlled based on the duty of that signal. note that the output is on when a low level is input to the pwmin pin, and off when a high level is input. when the pwmin pin is open it goes to the high level and the output is turned off. if inverted input logic is required, this can be implemented with an external transistor (npn). when controlling motor operation from the pwmin pin, the ei+ pin must be connected to the vreg pin. note that since the pwm oscillator is also used as the clock for internal circuits, a capacitor (about 2000pf) must be co nnected to the pwm pin even if the pwmin pin is used for motor control.
lb11620t no.a0662-12/11 5. hall input signals a signal input with an amplitude in excess of the hyster esis (80mv maximum) is required for the hall inputs. considering the possibility of noise and phase displacement, an even larger amplitude is desirable. if disruptions to the output waveforms (during phase switching ) or to the hp output (hall signal output) occur due to noise, this must be prevented by inserting capacitors acros s the inputs. the constraint protection circuit uses the hall inputs to discriminate the motor constraint state. although the circuit is designed to tolerate a certain amount of noise, care is required when using the constraint protection circuit. if all three phases of the hall input signal system go to the same input state, the outputs are all set to the off state (the u l, vl, wl, uh, vh, and wh outputs all go to the low level). if the outputs from a hall ic are used, fixing one side of the inputs (either the + or ? side) at a voltage within the common-mode input voltage range allows the other input side to be used as an input over the 0v to v cc range. 6. under-voltage protection circuit the under-voltage protection circuit turns one side of the outputs (uh, vh, and wh) off when the vreg pin voltage falls below the minimum operation voltage (see the electrical ch aracteristics). to prevent th is circuit from repeatedly turning the outputs on and off in the vicinity of the protection operating voltage, this circuit is designed with hysteresis. thus the output will not recover until the operating voltage rises 0.5v (typical). 7. constraint protection circuit when the motor is physically constrained (held stopped), the csd pin external capacitor is charged (to about 3.0 v) by a constant current of about 2.25 a and is then discharged (to about 1.0v) by a constant current of about 0.15 a. this process is repeated, generating a saw-tooth waveform. the constraint protection circuit turns motor drive on and off repeatedly based on this saw-tooth waveform. (the uh, vh, and wh side outputs are turned on and off.) motor drive is on during the period the csd pin external capacitor is being charged from about 1.0v to about 3.0v, and motor drive is off during the period the csd pin external capacitor is being discharged from about 3.0v to about 1.0v. the ic and the motor are protected by th is repeated drive on/off operation when the motor is physically constrained. the motor drive on and off times are determined by the value of the connected capacitor c (in f). tcsd1 (drive on period) 0.89 c (seconds) tcsd2 (drive off period) 13.3 c (seconds) when a 0.47 f capacitor is connected externally to the csd pin, this iterated operation will have a drive on period of about 0.4 seconds and a drive off period of about 6.3 seconds. while the motor is turning, the discharg e pulse signal (generated once for each hall input period) that is created by combining the hall inputs internally in the ic discharges the csd pin external capacitor. since the csd pin voltage does not rise, the constraint protection circuit does not operate. when the motor is physically constrained, the hall inputs do not change and the discharge pulses are not generated. as a result, the csd pin external capacitor is charged by a constant current of 2.5 a to about 3.0v, at which point the constraint protection circuit operates. when the constraint on the motor is released, the constraint protection function is released. connect the csd pin to ground if the constraint protection circuit is not used. 8. forward/reverse direction switching this ic is designed so that through currents (due to the output transistor off delay time when switching) do not flow in the output when switching directions when the motor is turnin g. however, if the direction is switched when the motor is turning, current levels in excess of the current limiter value may flow in the output transistors due to the motor coil resistance and the motor back emf state when switching. therefore, designers must consider selecting external output transistors that are not destro yed by those current levels or only switching directions after the speed has fallen below a certain speed. 9. handling different power supply types when this ic is operated from an externally su pplied 5v power supply (4.5 to 5.5v), short the v cc pin to the vreg pin and connect them to th e external power supply. when this ic is operated from an externally supplied 12v power supply (8 to 17 v), connect the v cc pin to the power supply. (the vreg pin will generate a 5v level to function as the control circuit power supply.)
lb11620t ps no.a0662-13/13 11. power supply stabilization since this ic uses a switching drive technique, the power su pply line level can be disturbed easily. therefore capacitors with adequate capacitance to stabilize the power supply line must be inserted between v cc and ground. if diodes are inserted in the power supp ly lines to prevent destruction if the power supply is connected with reverse polarity, the power supply lines are even more easily disrupted, and even larger capacitors are required. if the power supply is turned on and off by a switch, and if there is a significant distance between that switch and the stabilization capacitor, the supply voltage can be disrupte d significantly by the line indu ctance and surge current into the capacitor. as a result, the withstand voltage of the devi ce may be exceeded. in application such as this, the surge current must be suppressed and the voltage rise prevented by not using ceramic capacitors with a low series impedance, and by using electroly tic capacitors instead. 12. vreg stabilization to stabilize the vreg voltage, which is the control circuit power supply, a 0.1 f or larger capacitor must be inserted between the vreg pin and ground. the ground side of this capacitor must connected to the ic ground pin with a line that is as short as possible. on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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